1. Field of the Invention
This invention relates to Static Random Access Memories ("SRAMs"). In particular, it relates to a circuit which can be incorporated into a SRAM to simplify the detection of power supply short circuits within arrays of SRAM memory cells.
2. Description of the Relevant Art
A generic SRAM memory cell is shown in FIG. 1a. The construction and operation of such cells is known. In the illustrated cell, transistor T.sub.1 is the driver and transistor T.sub.3 the load for an inverter that is cross-coupled to a second inverter formed from transistors T.sub.2 and T.sub.4, the two inverters forming a storage flip-flop. When transistor T.sub.2 is on and transistor T.sub.1 is off, output Q is a logic 1 (herein, +5 V). With the row-select line low (0 V), transistors T.sub.5 and T.sub.6 are off, and the cell is isolated from both bit lines. When the memory cell is read, as soon as the row-select line goes high (+5 V), transistors T.sub.5 and T.sub.6 couple the bit lines to the cell and output Q appears on bit line D.
As shown in FIG. 1b, a sense amplifier is connected to the bit line to provide output buffering, and the proper logic level appears on the sense output line. In a write operation, the selected row of cells is connected to the bit lines, and Q or Q is set or reset by a logic 1 (+5 V) placed on bit line D or D by the write amplifiers while a logic 0 (0 V) is placed on the complement bit line. In this SRAM with nondestructive readout, the state of the flip-flop persists as long as power is supplied to the chip, and it is not altered by the read operation. It should be understood that an SRAM chip will comprise many thousands of such memory cells.
In normal operations, transistors T.sub.1 and T.sub.2 have a certain amount of capacitance, shown in FIG. 1a as capacitors C.sub.1 and C.sub.2. If V.sub.dd were shorted to V.sub.ss, due to a manufacturing error, a certain amount of time would be required before the charge present on either C.sub.1 and C.sub.2 (the nature of the flip-flop requires that either Q or Q be high (+5 V), but not both) is drained through transistors T.sub.3 and T.sub.4 to V.sub.ss. This discharge time is often large in comparison to the amount of time required to access the memory cell and the frequency of such access. It is therefore quite possible to read data several times from a cell with such a short circuit before the charge is dissipated sufficiently to detect the presence of the short.
This long dissipation time makes testing for this type of short circuit a long, tedious and costly process. A method and/or an apparatus which can speed the process of testing for and detecting such power supply short circuits is needed.